1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and to a semiconductor device.
Priority is claimed on Japanese Patent Application No. 2004-251809, filed Aug. 31, 2004, and on Japanese Patent Application No. 2005-114403, filed Apr. 12, 2005, the contents of which are incorporated herein by reference.
2. Description of Related Art
In recent years there have been demands for reductions in both the size and weight of portable electronic instruments such as mobile telephones, notebook type personal computers, and personal digital assistants (PDA). In conjunction with this, reductions in the size of various electronic components such as semiconductor devices that are provided inside these instruments have been achieved. This has led to the use of multichip packages in which a plurality of semiconductor chips are arranged inside a single package. In this case, by stacking a plurality of semiconductor chips in the thickness direction thereof, it is possible to obtain a higher semiconductor chip packaging density than when a plurality of semiconductor chips are lined up side by side. From this background, semiconductor chip three-dimensional packaging technology has been proposed. This three-dimensional packaging technology is a technology in which semiconductor chips that each have the same functions or else semiconductor chips that have different functions are stacked. For example, a method is known in which semiconductor chips that are provided with trans-substrate conductive plugs that are located on top of a chip substrate and terminals that are connected to these trans-substrate conductive plugs are stacked after a connection surface of the terminals has undergone activation processing (see, for example, Japanese Unexamined Patent Application, First Publication No. 2002-170919). However, in this method, because the semiconductor chips are constructed with the trans-substrate conductive plugs and the terminals being formed separately on top of the semiconductor chips, the semiconductor chips end up having a considerable size and it has been difficult to efficiently increase the packaging density.
As a result of this, a semiconductor chip has become known in which the packaging density has been improved by reducing the size of the semiconductor chips by forming the trans-substrate conductive plug and the terminal integrally with each other (see, for example, Japanese Unexamined Patent Applications, First Publication Nos. H10-223833 and 2000-277689). When the semiconductor chips are being stacked, they are stacked while terminals that are connected by a trans-substrate conductive plug being aligned. However, because the terminals that are above and below a trans-substrate conductive plug are the same size, when the semiconductor chips are being stacked, it is essential that there is no misalignment between the lower terminal and the upper terminal, so that this alignment of the positions of the semiconductor chips is difficult.
Therefore, a technology has been developed in which the active surface side (i.e., the surface on which an integrated circuit is formed) of a semiconductor chip and the size of the outer shape of the trans-substrate conductive plug that protrudes on the back surface side of the semiconductor chip are formed at different sizes (for example, see Japanese Unexamined Patent Application, First Publication No. 2003-282819. Specifically, the terminal on the active surface side is made larger than the terminal on the back surface side. Accordingly, when semiconductor chips are being stacked, by placing a large terminal in contact with a small terminal it becomes easy to align terminals of adjacent semiconductor chips.
Generally, in order to stack semiconductor chips on an interposer substrate (i.e., on a connecting body) they are bonded together via a solder (i.e., a brazing material) layer.
However, in a conventional manufacturing process for the aforementioned semiconductor chips that are provided with trans-substrate conductive plugs having different outer shapes, it is not possible to form a solder layer on the terminal of the interposer substrate. Accordingly, the solder layer has been formed on the trans-substrate conductive plug terminal that has a large outer shape and protrudes from the active surface side.
As a result, when the semiconductor chips are being stacked on an interposer substrate, they are stacked with the terminal on the active surface side where the solder layer is formed made to face downwards.
When a terminal on the active surface side is connected to the terminal of the interposer substrate, if pressure is applied while heat is supplied from the terminal on the back surface side, the solder layer provided on the terminal on the active surface side is melted and the semiconductor chips are bonded together. At this time, if the temperature at which the solder layers are bonded is too high, the insulating film covering the trans-substrate conductive plug is damaged. Therefore, it is desirable that the bonding temperature be approximately the temperature at which the solder layer melts. Moreover, because the terminals on the active surface side have a larger outer shape than the terminals on the back surface side, a large quantity of the solder layer needs to be melted in order to solder the semiconductor chip and the interposer substrate together.
However, if heat is applied at the melting temperature of the solder layer, then when the heat is conducted from the terminal on the back surface side to the terminal on the active surface, the heat conducts to peripheral portions of the terminal on the active surface side, which has a larger outer shape, and ends up being wasted. As a result, it is not possible for the entire solder layer on the terminal on the active surface side to be melted. Accordingly, in order to melt the entire solder layer, it is necessary to apply heat at a temperature that is sufficiently higher than the melting temperature of the solder layer. This raises the possibility that the aforementioned insulating layer covering the trans-substrate conductive plug will be damaged.
Moreover, for example, a semiconductor chip may be further stacked on top of the semiconductor chip that is stacked on the interposer substrate.
At this time, the solder layer that is provided on the terminal on the active surface side forming the second layer forms an alloy layer at a boundary with the terminal. Accordingly, as the heat to melt the solder layer is first conducted to the alloy layer, the solder layer on the terminal on the active surface side ends up being consumed in the formation of a further solder layer.
Furthermore, when the semiconductor chips are compressed, the terminal on the back surface side of the semiconductor chip forming the first layer are pressed into the solder layer so as to push away the solder layer to peripheral portions of the terminal on the active surface side. As a result, the quantity of solder that is located between the terminal on the active surface side and the terminal on the back surface side is reduced, and there is a possibility that a satisfactory solder bond will not be possible.
Moreover, because the semiconductor chips are stacked with the terminal on the active surface side on which the solder layer is formed facing downwards, when the solder is melted, the solder is influenced by gravity and droops down. If this solder then makes contact with the semiconductor chip provided on the layer beneath it, there is a possibility of short-circuiting occurring.
In recent years, technology has also become established for forming a solder layer on the terminal on the interposer substrate.